It is known in an analog-digital conversion apparatus that jitter included in an input sampling clock will vary the sampling phase of the signal to be converted and deteriorate conversion accuracy. To suppress the deterioration in conversion accuracy due to jitter, a method is generally employed which uses an oscillator with low jitter to generate the sampling clock. In addition, Patent Document 1, for example, proposes a method of correcting the deterioration due to jitter after converting a signal to be converted to a digital signal.
On the other hand, the same deterioration in conversion accuracy due to jitter occurs in a digital-analog conversion apparatus as well. With this apparatus, the period over which the analog value is maintained at a fixed value is identical to the period of the sampling clock. Thus, the period over which the analog value is maintained at a fixed value fluctuates owing to jitter, and spurious frequency components are superimposed, thereby deteriorating the conversion accuracy. In this case also, to reduce the deterioration in conversion accuracy, a method is generally employed which uses an oscillator with low jitter to generate the sampling clock.
Patent Document 1: Japanese patent laid-open No. 4-150354/1992.
Although the conventional analog-digital conversion apparatus and digital-analog conversion apparatus employ the foregoing methods to reduce the deterioration in conversion accuracy, they have a problem of increasing cost because of the high accuracy required when using the oscillator with low jitter. In addition, the method described in Patent Document 1 has a problem of requiring a configuration for carrying out complicated digital processing to correct the deterioration in conversion accuracy.
The present invention is implemented to solve the foregoing problems. Therefore it is an object of the present invention to provide an analog-digital conversion apparatus and a digital-analog conversion apparatus capable of preventing the deterioration in the conversion accuracy even if the sampling clock includes jitter.